1. Field of the Invention
The present invention generally relates to processes for fabricating metal oxide semiconductor field effect transistor (MOSFET) structures and more particularly to MOSFET structures which include lightly doped polysilicon gates, operating at high operating voltages, and MOSFET structures which include more heavily doped polysilicon gate structures which operate at low operating voltages.
2. Description of the Related Art
As the gate oxide thickness decreases in today's advanced complementary metal oxide semiconductor (CMOS) technologies, the maximum voltage (Vmax) allowed across the gate oxide also decreases. The decrease in Vmax makes interfacing with technologies which have higher supply voltages more difficult.
Conventional solutions to interface with technologies which have higher supply voltages include using circuit techniques to step down the voltage which is seen across the oxide and creating a dual oxide process which supports a higher Vmax. Using circuit techniques to step down the voltage increases circuit complexity and decreases overall chip speed. Using a dual oxide process increases the processing cost and complexity.
Conventional methods form multiple CMOS devices on a single wafer. Each of the CMOS devices includes a polysilicon gate and a thin gate oxide between the polysilicon gate and the substrate. Ions are implanted to dope the polysilicon gate and the adjacent source and drain structures.
Selected polysilicon gates are protected with a sacrificial layer and the remaining polysilicon gates are subjected to a lightly doped ion implantation. Conventional processes then dope other polysilicon gates using a heavier source-drain implant. In the second ion implantation step, the lightly doped polysilicon gates are protected with another sacrificial layer and the exposed polysilicon gates are subject to the second ion implantation.
This repetitive masking-implantation process produces some polysilicon gates with lighter doping and other polysilicon gates with heaver doping. The blocking of the second ion implantation produces lightly doped gates in the blocked devices, which are sometimes referred to as poly depleted gates. The lightly doped or undoped polysilicon gates accommodate higher voltages.
While such conventional methods simultaneously produce CMOS chips which can handle high voltages and CMOS chips which can handle low voltages, these methods require additional processing steps to deposit and remove sacrificial layers and require additional implantation steps which are avoided by the invention.